1. Field of the Invention
The present invention relates to analysis of integrated circuits, and more particularly concerns determination of failure criteria for thin metallic film conductors.
2. Description of Related Art
Electromigration of atoms and ions is of major concern with respect to reliability and failure of integrated circuits. Under stress due to flow of electrical current and temperature, atoms and ions of metal, such as aluminum atoms or ions, of thin interconnect metallic conductors laid down on a semiconductor substrate actually move through the structure of the metal. This movement, or electromigration, from one point to another within the metal structure may cause either a void at the position originally occupied by the moving atom or a deposition or growth at one area of the metal. It has been determined that in many configurations of integrated circuits void formation is the defect most likely to decrease the life of the circuit or to result in failure. The metallic interconnect lines on the integrated circuit are very thin and very narrow, in the order of just a few micro meters for example, so that electromigration may induce a void that results in a significant narrowing of the electrically conductive material across the width or thickness of the conductive line. Decreased width of the line will tend to cause failure over a much shorter life or may in fact result in an open line. Therefore, it is highly desirable to be able to characterize electromigration properties of an interconnect metal line so as to determine a median life time to failure (MTTF), the activation energy (Ea) of grain boundary diffusion and the current density dependance or current density exponent (N).
In the past such electromigration criteria have been obtained through conventional DC electromigration tests performed on a completely packaged chip but with greatly enhanced or exaggerated current densities (in the order of about one million amps per square centimeter) and at elevated temperatures (in the order of about 150.degree. C. to 250.degree. C.). Such tests have been performed such that resistance of the line under test increases by about thirty percent, thus indicating a line of decreased width, because the resistance increases as the width decreases due to a void or similar defect. Elapsed time for this amount of resistance increase to occur was measured. Under this prior art test a number of measurements are made at various temperatures and at various current densities to obtain data sufficient to solve for unknown values of Ea (activation energy), N (current density exponent) and A (a proportionality constant) in Black's equation, which is as follows: EQU MTTF=A(J).sup.-N exp (Ea/KT) Equation (1)
where K is the Boltzmann constant, T is temperature, J is current density, and MTTF is the mean time to failure in years. At each of the several different current densities resistance is measured and the value of MTTF at a point where the resistance increases by thirty percent is employed to solve for the quantities Ea, N and A. Then, utilizing the highest actual temperature and current density expected to be encountered during actual operation, the value of MTTF is calculated by Black's equation, Equation (1), to provide a measure of the life of the equipment or integrated circuit under observation. In these prior tests temperature is measured temperature of the integrated circuit.
A major problem associated with this prior art testing is that the test is conducted after the complete assembly of the chip. In the normal semiconductor chip manufacture, a large number of chips are formed on a single semiconductive wafer, and there are a sufficient number of steps taken subsequent to the formation of the chips on the wafer in the assembly of a final chip that a long time may elapse before the final structure is completed and ready for this testing. This means that all of the subsequent manufacturing steps and assembly must be completed and assembly must be at least partially complete before this type of lifetime testing can be made to determine whether or not the metal interconnect layers are or are not satisfactory.
Further, the prior DC current flow test employs externally generated temperature to heat the conductive material under test well above room temperature and utilizes a high resistance change, as much as thirty percent increase in resistance, as the estimated failure point. These conditions and features of the prior tests introduced errors in measurement, as will be discussed below.
Several wafer level electromigration test methods have been proposed utilizing the wafer prior to the full assembly of the packaged chip. Unlike the conventional test, these methods use considerably higher current density and higher temperature to actually attempt to accelerate the electromigration phenomenon in the thin metal films. The advantage of these methods is the greatly shortened testing period. These methods include those known as TRACE, SWEAT, Isothermal and BEM, as described in references 1 through 4 appended to the end of this written description. In the TRACE technique resistance change is monitored during a constant current ramped temperature test in which temperature is continuously increased. Resistance change in the metal line is attributed to the electromigration effect. The disadvantage of using this method is that the external temperature source, which supplies an increasing temperature, may affect the neighbor test structure on the same die or wafer. Further, this test is not applicable for use as an on-line process monitor.
BEM (breakdown energy of metal) utilizes a ramp or increasing current without external temperature source to monitor the quality of metalization. This test is limited by its requirement of a previous known activation energy of the metal for calculation. Therefore, this method does not allow derivation of the properties of electromigration such as Ea, A and N for an unknown material.
Isothermal test, as reported in Reference 3, involves a computer reading of multi meters and calculates sample resistance used in a feedback loop to control power supply voltage such that the temperature sample can be kept constant. The ability of this method to obtain accurate measurement is questionable.
SWEAT (standard wafer level electromigration accelerated test), as reported in Reference 2, attempts to achieve a constant acceleration factor using known Ea and N. This test has successfully demonstrated measurement of relative metal quality but fails to adequately explain failure mechanisms, and thus can only be employed with a catastrophic failure.
Patents related to the problem of electromigration and integrity of thin film interconnect lines of integrated circuits include the following: U.S. Pat. No. 4,483,629, 4,739,258, 4,213,087, 3,474,530, 4,816,895, 4,897,709 and 5,148,259. None of these patents, nor any of the methods, are capable of demonstrating an ability to identify failure mechanisms or to measure basic electromigration properties.
Accordingly, it is an object of the present invention to provide for determination of failure criteria in metal alloy films in a manner that avoids or eliminates above mentioned problems.